Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 956

DAI Signal Routing Unit Registers
31 30
IDP2_FS_I (29–25)
Input Data Port Channel 2
Frame Sync Input
15
IDP0_FS_I or
PDAP_HOLD_I
(19–15)
DIT_FS_I (14–10)
SPDIF 3 Oversampling
Clock Input
Figure A-67. SRU_FS2 Register (RW)
31 30
IDP7_FS_I (24–20)
Input Data Port
Channel 7 Frame Sync Input
15
IDP6_FS_I (19–15)
IDP5_FS_I (14–10)
Input Data Port Channel 5
Frame Sync Input
IDP4_FS_I (9–5)
Input Data Port Channel 4
Frame Sync Input
Figure A-68. SRU_FS3 Register (RW)
15
SPORT7_FS_I (9–5)
Serial Port 7 Frame Sync Input
Figure A-69. SRU_FS4 Register (RW)
A-130
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29 28 27 26 25 24
14 13 12 11 10 9 8 7
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
14 13 12 11 10 9 8 7
ADSP-214xx SHARC Processor Hardware Reference
23 22 21 20 19 18 17 16
6 5 4 3 2 1 0
21 20 19 18 17 16
6 5 4 3 2 1 0
6 5 4 3 2 1 0
IDP0_FS_I or
PDAP_HOLD_I (19–15)
(con't)
Input Data Port Channel
0 Frame Sync Input
IDP1_FS_I (24–20)
Input Data Port Channel 1
Frame Sync Input
SRC3_FS_IP_I (4–0)
Sample Rate Converter 3
Frame Sync Input Input
SRC3_FS_OP_I (9–5)
Sample Rate Converter 3
Frame Sync Output Input
IDP6_FS_I (19–15) (con't)
Input Data Port
Channel 6 Frame Sync Input
IDP3_FS_I (4–0)
Input Data Port
Channel 3 Frame Sync Input
SPORT6_FS_I (4–0)
Serial Port 6 Frame
Sync Input