Dma Access; Chained Dma; Core Access - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

DMA Access

A link port interrupt is generated when the DMA operation is done—
when the block transfer has completed and the DMA count register is
zero.
One way programs can use this interrupt is to send additional control
information at the end of a block transfer. Because the receive DMA buf-
fer is empty when the DMA block has completed, the external bus master
can send up to two additional words to the slave processor's buffer, which
has space for the two words. When the slaves's DMA completes, there is
an interrupt. In the associated interrupt service routine, the buffer can be
read in order to use these control words to determine the next course of
action.

Chained DMA

In chained DMA operations, the processor automatically sets up another
DMA transfer when the current DMA operation completes. The chain
pointer register points to the next set of DMA parameters stored in the
processor's internal memory. Each new set of parameters is stored in a four
word, user-initialized buffer in internal memory known as a transfer con-
trol block (TCB). In TCB chain loading, the processor's IOP
automatically reads the TCB from internal memory and then loads the
values into the channel parameter registers to set up the next DMA
sequence. The chain pointer can be loaded at any time during the DMA
sequence. Writing all zeroes to the address field of the chain pointer also
disables chaining.

Core Access

If DMA is disabled for a link port buffer, then the buffer may be written
or read by the processor core as a memory-mapped I/O processor register.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Link Ports—ADSP-2146x
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