Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 388

Operation Modes
Center-Aligned Non-Paired Mode. Generates independent signals on two
outputs.
In paired mode, the two's-complement integer values in the 16-bit
read/write duty cycle registers,
the four PWM output signals on the
pins respectively. The duty cycle registers are programmed in two's-com-
plement integer counts of the fundamental time unit,
desired on time of the high side PWM signal over one-half the PWM
period.
The duty cycle register range is from (–PWMPERIOD/2 – PWMDT) to
(+PWMPERIOD/2 + PWMDT), which, by definition, is scaled such that
a value of 0 represents a 50% PWM duty cycle.
Each group in the PWM module (0–3) has its own set of registers which
control the operation of that group. The operating mode of the PWM
block (single or double update mode) is selected by the
2) in the PWM control (
each individual PWM group is available to the program in the PWM sta-
tus (
PWMSTAT3–0
for each PWM group, there is a single PWM global control register
( ) and a single PWM global status register (
PWMGCTL
control register allows programs to enable or disable the four groups in
any combination, which provides synchronization across the four PWM
groups.
The global status register shows the period completion status of each
group. On period completion, the corresponding bit in the
ister is set and remains sticky. The program first reads the global status
register and clears all the intended bits by explicitly writing 1.
7-20
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PWMAx
PWMCTRL3–0
) registers. Apart from the local control and status registers
ADSP-214xx SHARC Processor Hardware Reference
and , control the duty cycles of
PWMBx
, ,
PWM_AL PWM_AH PWM_BL
PCLK
PWM_UPDATE
) registers. Status information about
PWMGSTAT
and
PWM_BH
and define the
bit (bit
). The global
reg-
PWMGSTAT