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IIR Accelerator
The 40-bit wide debug mode write data register is organized as:
• The
IIRDBGWRDATA_L
• The
IIRDBGWRDATA_H
A read from the
IIRDBGRDDATA_H
tion pointed to by the address register. Data can be written into any
memory location using the
IIRDBGWRDATA_H
If the address auto increment bit (
auto increments on
During auto increment, the
memory/coefficient memory boundary. The address boundary for data
memory is 1024 locations and for coefficient memory 2048 locations
Single Step Mode
Programs can single step through the MAC operations and observe the
memory contents after each step. The
bits control the IIR MAC units.
Emulation Considerations
In IIR debug mode, the DMA operations are not observable.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
6-66
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register holds the lower 32 bits and
register holds the upper 8 bits
register followed by a read from the
IIRDBGRDDATA_L
register returns the content of the 40-bit memory loca-
IIRDBGWRDATA_L
register.
IIR_ADRINC
IIRDBGWRDATA_H
IIR_DBGADDR
ADSP-214xx SHARC Processor Hardware Reference
register followed by the
) is set, the address register
/
writes and
L
IIRDBGRDDATA_H
register cannot cross the data
/
IIR_DBGMODE
IIR_HLD
/
reads.
L
and
IIR_RUN
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