Processing Output - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

FIR Accelerator

Processing Output

The accelerator uses all four MACs simultaneously to calculate one output
sample as shown in
DMA partial sum
from output
buffer OR load 0 if
first iteration
Figure 6-5. Multi-Iteration Filtering Flow
6-34
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Figure 6-5 and the following procedure.
Load chain pointer and control registers
and enable accelerator
Load coefficients for
the iteration
Prefill delay line
Load next data
Perform all MACS
and calculate result
Add partial sum
to the result
DMA Computed
result to output
Is this the
NO
last data for this
iteration?
YES
Is this the
NO
last iteration?
YES
Raise channel
complete interrupt
ADSP-214xx SHARC Processor Hardware Reference
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