Address Mapping - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table 3-5. SDRAM Pin States During SDC Commands
Command SDCKE
(n–1)
Mode 1
register set
Activate 1
Read 1
Single 1
Precharge
Precharge all 1
Write 1
Auto-refresh 1
Self-refresh 1
entry
Self-refresh 0
Self-refresh 0
exit
Nop 1
Inhibit 1

Address Mapping

To access SDRAM, the controller multiplexes the internal 32-bit
non-multiplexed address into three portions:
• Row address bits
• Column address bits
• Bank address bits
The non multiplexed address that is seen from the core/DMA is referred
to as IA31–0 in the following sections.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
SDCKE MS3–0 SDRAS SDCAS SDWE
(n)
1 0 0
1 0 0
1 0 1
1 0 0
1 0 0
1 0 1
1 0 0
0 0 0
0 X X
1 1 X
1 0 1
1 1 X
External Port
SDA10
0 0 Opcode
1 0 Valid
0 1 0
1 0 0
1 0 1
0 0 0
0 1 X
0 1 X
X X X
X X X
1 1 X
X X X
Addresses
Opcode
Valid
Valid
Valid
X
Valid
X
X
X
X
X
X
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