Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 652

Programming Model
3. Disable DMA and clear the DMA FIFO by setting the
bit is the
vious DMA operation is cleared because the
five more word transfers even after the DMA count falls to zero in
the receive DMA.
4. Clear all errors by writing to the
that no interrupts occur due to errors from a previous DMA
operation.
5. Reconfigure the
6. Configure DMA by writing to the DMA parameter registers and
the
SPIDMACx
With enabled SPI:
1. Poll the
be disabled.
2. Clear the
abling the SPI by ORing 0xC0000 with the present value in the
SPICTLx
in the
SPICTLx
the buffer status.
3. Clear the DMA FIFO by the
without changing other bits. This ensures that any data from a pre-
vious DMA operation is cleared because
word transfers even after the DMA count is zero in receive DMA.

The
SPIDMACx
will change the DMA direction and cause bad data to be transmit-
ted out, even with DMA disabled.
4. Clear all errors by writing to the W1C-type bits in the
registers. This ensures that no interrupts occur due to errors from a
previous DMA operation.
15-36
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registers. This ensures that any data from a pre-
SPIDMACx
registers and enable the SPI.
SPICTLx
registers using the
bit in the
SPIFE SPISTAT
/ registers and the buffer status without dis-
RXSPIx TXSPIx
registers. Use the
RXFLSH
registers to clear the
register bits should not be changed because as this
ADSP-214xx SHARC Processor Hardware Reference
SPICLK
registers. This ensures
SPISTATx
bit (bit 0).
SPIDEN
register. If this bit =1 the SPI can
(bit 19) and
TXFLSH
RXSPIx/TXSPIx
bit in the
FIFOFLSH
runs for five more
SPICLK
FIFOFLSH
signal runs for
(bit 18) bits
registers and
register
SPIDMACx
SPISTATx