Channel Order First - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Operation Modes
control (
SPCTLx
cific SPORT operation mode. The shaded columns indicate that the bits
come from different control registers.
Table 10-7. SPORT Operation Modes
OPERATING MODES
(x = A or B or A and B
SPORT Channels)
Standard Serial Mode
Left-justified Mode
2
I S Mode
Packed Mode
Multichannel Mode
The following sections provide detailed information on each operating
mode available using the serial ports. It should be noted that many bits in
the SPORT registers that control the function of the mode are the same
bit but have a different name depending on the operating mode. Further,
some bits are used in some modes but not others. For reference, see
Table 10-6 on page
page A-150.

Channel Order First

For left-justfied, I
word is transmitted or receive first depending on the
10-24
www.BDTIC.com/ADI
) registers that must be set in order to configure each spe-
OPMODE OPMODE
(Bit 11) (Bit 17)
0
1
1
1
0
10-22, Table 10-7, and
2
S and packed modes the next table demonstrates which
ADSP-214xx SHARC Processor Hardware Reference
SPCTLx Bits
SPEN_x
(Bit 0/24)
Valid 1
1 1
0 1
0 0
0 0
"Serial Port Registers" on
L_FIRST
SPMCTLx Bits
MCEx
0
0
0
1
1
bit.