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External Port
This context-dependent caching preserves the cache performance of the
traditional SHARC conflict cache as well as significantly improving pro-
gram instruction throughput for repetitive instructions such as those
inside loops when executing from external memory. Analyses of typical
application code examples have shown that this 32-entry instruction cache
improves execution throughput by 50-80% over not having this cache.
In general, cache hits occur for all instructions which are fetched and exe-
cuted multiple times (for example loops, subroutine calls, negative
branches, and so on). Typical applications, such as signal processing algo-
rithms, are ideal candidates for significant performance improvements as a
result of the cache.
An important and significant result of the instruction being fetched from
the cache is that it frees up the external port as well as the internal PM and
DM buses for other operations such as data transfers, operand fetches, or
DMA transfers.
The following example shows the innermost loop of a FIR filter.
lcntr=FILTER_TAPS-1, do macloop until lce;
macloop: f12=f0*f4, f8=f8+f12, f0=dm(i0,m1), f4=pm(i9,m9);
In this example, if the code is stored and executed from external memory,
the first time through this loop the program sequencer places the appro-
priate 24-bit address on the external address bus, and fetches the
instruction in line 2 from external memory. While this instruction is being
fetched and processed by the sequencer, it is also simultaneously stored in
the internal instruction cache.
For every subsequent iteration of this loop, the instruction is fetched from
the internal cache, thereby occurring in a single cycle, while freeing up the
internal memory buses to fetch the data operands required for the
instruction.
Previously, in the absence of the internal instruction cache, the number of
cycles taken by the loop for a case of
= 16 would have been a
FILTER_TAPS
ADSP-214xx SHARC Processor Hardware Reference
3-97
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