Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 567

16
GDS = ------------------------------ - +
SRCx_FS_IP
Decimation Rate
The RAM in the FIFO is 512 words deep for both left and right channels.
An offset to the write address provided by the f
prevent the RAM read pointer from ever overlapping the write address.
The offset is fixed by the group delay signal. A small offset, 16, is added to
the write address pointer.
Increasing the offset of the write address pointer is useful for applications
when small changes in the sample rate ratio between f
are expected. The maximum decimation rate can be calculated from the
RAM word depth and GRPDLYS as (512 – 16)/64 taps = 7.75:1.
Muting Modes
The mute feature of the SRC can be controlled automatically in hardware
using the
MUTE_IN
matic muting can be disabled by setting (=1) the
register.
SRCMUTE

Note that by default, the
nal to the
Soft Mute
When the
SRCx_SOFTMUTE
nal is asserted, and the SRC performs a soft mute by linearly decreasing
the input data to the SRC FIFO to zero, (–144 dB) attenuation as
described for automatic hardware muting.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Asynchronous Sample Rate Converter
  
32 SRCx_FS_IP
×
------------------------------ - -------------------------------- -
  
SRCx_FS_IP SRCx_FS_OP
signal by connecting it to the
SRCMUTE
signal, but not vice versa.
MUTE_OUT
bit in the

(
sec onds for SRCx_FS_OP SRCx_FS_IP

_IN counter is added to
S
_IN and f
S
MUTE_OUT
SRCx_MUTE_EN
register connects the
register is set, the
SRCCTL
≤ )
_OUT
S
signal. Auto-
bits in the
sig-
MUTE_IN
sig-
MUTE_IN
12-15