Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 844

ADSP-2146x External Port Registers
Running Reset Control Register (RUNRSTCTL)
The
RUNRSTCTL
and is described in
Table A-7. Running Reset Control Register Bit Descriptions (RW)
Bit
0
1
31–2
ADSP-2146x External Port Registers
The registers in the following sections are specific to the ADSP-2146x
external port and include the external port, the DDR2 controller, and
AMI registers.
External Port Control Register (EPCTL)
The following registers are used to control asynchronous memory inter-
face (AMI), the DDR2 and SDRAM controllers, and the shared memory
interface. The external port control register can be programmed to arbi-
trate the accesses between the processor core and DMA, and between
different DMA channels. These registers are shown in
described in Table
A-18
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register is used to control the running reset functionality
Table A-7.
Name
PM_RUNRST_PINEN
PM_RUNRST_EN
Reserved
A-8.
ADSP-214xx SHARC Processor Hardware Reference
Description
Configures the RESETOUT pin for RUNRST
input.
0 = pin is
RESETOUT RESETOUT
1 = pin is RUNRST input
RESETOUT
Enable the Running Reset Functionality. If this
bit is cleared, attempting to cause a running reset
by toggling the
RUNRSTIN
0 = Running reset disabled
1 = Running reset enabled
Figure A-6
pin has no affect
and