Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 83

Table 2-2. Index Registers (Cont'd)
Register Name
OIIIR
IIFFT
OIFFT
IIMTMW
IIMTMR
IIEP0–1
EIEP0–1
Modify registers. These registers, shown in
increment by which the DMA controller post-modifies the corresponding
memory index register after the DMA read or write.
Table 2-3. Modify Registers
Register Name
IMSP0–7A
IMSP0–7B
IMSPI
IMSPIB
IDP_DMA_M0–7
IDP_DMA_M0–7A
IDP_DMA_M0–7B
IMLB0–1
IMUART0RX
IMUART0TX
IMFIR
CMFIR
OMFIR
ADSP-214xx SHARC Processor Hardware Reference
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Width (Bits) Description
19 Accelerator IIR output
19 Accelerator FFT input
19 Accelerator FFT output
19 MTM Write
19 MTM Read
19 External Port0–1
28 External Port (external)
Width (Bits) Description
16 SPORTA
16 SPORTB
16 SPI
16 SPIB
6 IDP
6 IDP modify A (ping pong)
6 IDP modify B (ping pong)
16 Link Port
16 UART0 Receiver
16 UART0 Transmitter
16 Accelerator FIR data input
16 Accelerator FIR coeff input
16 Accelerator FIR output
I/O Processor
Table 2-3, provide the signed
2-5