Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 583

Table of Contents

In SCDF mode, the transmitter sends successive audio samples of the

same signal across both sub frames, instead of channel A and B. The trans-

mitter will transmit at half the sample rate of the input bit stream. The

bit (bit 4 in the

SCDF mode, the

decides whether left or right channel data is transmitted.

S/PDIF Receiver

The S/PDIF receiver

digital audio interface standards including IEC-60958, IEC-61937,

AES3, and AES11. These standards define a group of protocols that are

commonly associated with the S/PDIF interface standard defined by

AES3, which was developed and is maintained by the Audio Engineering

Society. The AES3 standard effectively defines the data and status bit

structure of an S/PDIF stream. AES3-compliant data is sometimes

referred to as AES/EBU compliant. This term highlights the adoption of

the AES3 standard by the European Broadcasting Union.

Functional Description

The S/PDIF receiver is enabled at default to receive in two-channel

mode. If the receiver is not used, programs should disable the

receiver as the digital PLL may produce unwanted switching noise.

If the receiver is not used, programs should disable the digital PLL to

avoid unnecessary switching. This is accomplished by writing into the

receiver is used, this register does not need to be changed. After the SRU

programming is complete, write to the

At this point, the receiver attempts to lock.

For a detailed description of this register, see

(DIRCTL)" on page

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

bit (bit 5 in the

13-8) is compliant with all common serial

Sony/Philips Digital Interface

"Receive Control Register

Chapters

Table of Contents