Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 869

DDR2 Pad Control Register 0 (DDR2PADCTL0)
The
DDR2PADCTL0
Table A-23 includes the programmable parameters associated with the
DDR2 ,
DATA DQS
31 30
DDR2CLK_PWD
Receiver Power Down
15
Figure A-18. DDR2PADCTL0 Register
Table A-23. DDR2PADCTL0 Register Bit Descriptions (RW)
Bit Name
8–0 Reserved
9 DATA_PWD
18–10 Reserved
19 DQS_PWD
28–20 Reserved
29 DDR2CLK_PWD Clock Pad Receiver Power Down.
31–30 Reserved
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register shown in
and pads.
DDR2CLK
29 28 27 26 25 24
14 13 12 11 10 9 8 7
Description
Data Pad Receiver Power Down.
0 = Normal mode
1 = Power-down mode
DQS Pad Receiver Power Down.
0 = Normal mode
1 = Power-down mode
0 = Normal mode
1 = Power-down mode
Registers Reference
Figure A-18 and described in
23 22 21 20 19 18 17 16
6 5 4 3 2 1 0
DQS_PWD
Receiver Power Down
DATA_PWD
Receiver Power Down
A-43