Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 946

DAI Signal Routing Unit Registers
31 30
DIT_HFCLK_I (29–25)
SPDIF Oversampling Clock Input
15
IDP6_CLK_I (19–15)
IDP5_CLK_I (14–10)
Input Data Port Channel 5 Clock Input
Figure A-55. SRU_CLK3 Register (RW)
31 30
PCG_SYNC_CLKB_I (29–25)
Precision Clock Generator
Clock B Sync Input
DIT_EXT_SYNC_I (19–15)
SPDIF_EXTPLLCLK_I (14–10)
External 512 x FS PLL Clock Input
Figure A-56. SRU_CLK4 Register (RW)
A-120
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29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
29 28 27 26 25 24
15 14 13 12 11 10 9 8
ADSP-214xx SHARC Processor Hardware Reference
21 20 19 18 17 16
6 5 4 3 2 1 0
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1
IDP6_CLK_I (con't) (19–15)
Input Data Port Channel
6 Clock Input
IDP7_CLK_I (24–20)
Input Data Port Channel
7 Clock Input
IDP3_CLK_I (4–0)
Input Data Port Channel
3 Clock Input
IDP4_CLK_I (9–5)
Input Data Port Channel
4 Clock Input
DIT_EXT_SYNC_I (19–15)
S/PDIF Transmitter Clock
Input
PCG_SYNC_CLKA_I
Precision Clock Generator
Clock A Sync Input
0
PCG_EXTA_I (4–0)
Precision Clock Generator
External Clock A Input
PCG_EXTB_I (9–5)
Precision Clock Generator
External Clock B Input