Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 334

FIR Accelerator
In this example, the FIR controller implements two iterations of 256 taps
and one iteration of 38 taps.

Multi-iteration mode is not supported in fixed-point format.
Window Processing
Sample based processing mode is selected by configuring window size to 1.
In this mode, one sample from a particular channel is processed through
all the biquads of that channel and the final output sample is calculated.
In window based mode, multiple output samples (up to 1024) equal to the
window size of that channel are calculated. After these calculations are
complete, the accelerator begins processing the next channel. A configu-
rable window size parameter is provided to specify the length of the
window.
Multi Rate Processing
Multi rate filters change the sampling rate of a signal—they convert the
input samples of a signal to a different set of data that represents the same
signal sampled at a different rate.
Decimation
A decimation filter provides a single output result for every M input sam-
ples, where M is the decimation ratio. Note that the output rate is 1/M'th
of the input rate. The filter implementation exploits the low output sam-
ple rate by not starting a computation until a new set of M input samples
is available.
In this mode, after low pass filtering (for anti aliasing), FIR logic discards
the ratio – 1 samples of output data. For performance optimization, FIR
logic skips the computation of output samples, which are discarded.
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ADSP-214xx SHARC Processor Hardware Reference