Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 751

rates and peripheral bus access times, a double byte transfer data access can
be performed. Two data bytes can be written, effectively filling the trans-
mit FIFO buffer with a single access.
The data is written in little-endian byte order where byte 0 is the first byte
to be transferred and byte 1 is the second byte to be transferred. With each
access, the transmit status (
updated. If an access is performed while the FIFO buffer is not empty, the
core waits until the FIFO buffer is completely empty and then completes
the write access.
XMTDATA16 (23–16)
Byte1–Transmitted second
Figure 21-8. 16-Bit Transmit FIFO Register
8-Bit Receive FIFO Register
The TWI 8-bit FIFO receive register (
an 8-bit data value read from the FIFO buffer. Receive data is read from
the corresponding receive buffer in a first-in, first-out order. Although
peripheral bus reads are 32 bits, a read access to the
only access one receive data byte from the FIFO buffer. With each access,
the receive status (
an access is performed while the FIFO buffer is empty, the core waits until
there is at least one byte in the receive FIFO buffer and then completes the
read access.
15 14 13 12 11 10 9 8
Figure 21-9. 8-Bit Receive FIFO Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
) field in the
TWITXS
15 14 13 12 11 10 9 8
) field in the
TWIRXS
7 6 5 4 3 2 1 0
Two Wire Interface Controller
TWIFIFOSTAT
7 6 5 4 3 2 1 0
) shown in Figure 21-9
RXTWI8
RXTWI8
register is updated. If
TWIFIFOSTAT
RCVDATA8 (7–0)
Receive FIFO 8-bit Data
register is
XMTDATA16 (7–0)
Byte0–Transmitted first
holds
register can
21-13