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Internal DDR2 Bank Access
The following sections describe the different scenarios for DDR2 bank
access.
Single Bank Access
The DDR2 controller keeps only one page open at a time if all subsequent
accesses are to the same row or another row in the same bank.
Multibank Access
The processors are capable of supporting multibank operation, thus taking
advantage of the DDR2 architecture.
Operation using single versus multibank accesses depends only on
the address to be posted to the device, it is NOT an operation
mode.
Any first access to DDR2 bank (A) forces an activate command before a
read or write command. However, if any new access falls into the address
space of the other banks (B, C, D, E, F, or H) the controller leaves bank
(A) open and activates any of the other banks (B, C, D, E, F, or H). Bank
(A) to bank (B) active time is controlled by t
until all eight banks (A–H) are opened and results in an effective page size
of up to eight pages. This is because the absence of latency allows switch-
ing between these open pages (as compared to one page in only one bank
at a time). Any access to any closed page in any opened bank (A–H) forces
a precharge command only to that bank. If, for example, two external port
DMA channels are pointing to the same internal DDR2 bank, this always
forces precharge and activation cycles to switch between the different
pages. However, if the two external port DMA channels are pointing to
different internal DDR2 banks, there is no additional overhead. See
Figure
3-16.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
External Port
. This scenario is repeated
RRD
3-71
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