Intercommunication - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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5. Receiver accepts the remaining word even if

transmitter does not send the following word.

6. Transmit data for next word is held until

The receive buffer may fill if a higher priority DMA, core I/O processor

may deassert when it anticipates the buffer may fill. The

reasserted by the receiver as soon as the internal DMA grant signal has

occurred, freeing a buffer location or the core reads the receive buffer

thereby freeing a buffer location. The

mission of next word and not of the current byte.

Data is latched in the receive buffer on the falling edge of

The receive operation is purely asynchronous and can occur at any

frequency up to 166 MHz or peripheral clock frequency (which-

ever is less).

When a link port is not enabled,

three-stated. When a link port is enabled to transmit, the data pins are

driven with whatever data is in the output buffer,

is three-stated. When a port is enabled to receive, the data pins and

are three-stated and

Intercommunication

The transmitter and the receiver may be enabled at different times. The

resistors. If the transmitter is enabled before the receiver, the

(of the receiver) is held low and transmission is held off. If the receiver is

enabled before the transmitter, the

low by the pull-down and the receiver is held off.

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

is driven high.

signals should be held low with the external pull-down

Link Ports—ADSP-2146x

is deasserted. The

is asserted.

signal inhibits trans-

is driven high and

signal (of the transmitter) is held

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