Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 804

Processor Booting
Table 23-11 shows the link port control settings after reset.
Table 23-11. LPCTL0 Boot Settings (0x403)
Bit
0
1
2
3
7
8
9
10
11
12
The DMA parameters for the Link Port0 channel are configured as shown
in Table 23-12.
Table 23-12. Parameter Initialization for Link Boot
Parameter Register
Elf splitter
IILP0
IMLP0
ICLP0
23-22
www.BDTIC.com/ADI
Name
LEN
LDEN
LCHEN
LTRAN
BHD
LTRQ_MSK
LRRQ_MSK
DMACH_IRPT_MSK
LPIT_MSK
TXFR_DONE_MSK
Initialization Value
IVT_START_ADDR
0x1
0x180
ADSP-214xx SHARC Processor Hardware Reference
Setting
Link port enabled (set = 1)
DMA enabled (set = 1)
DMA Chaining (cleared = 0)
Receive operation (cleared = 0)
Buffer hang disabled (cleared = 0)
LP transmit request mask (cleared = 0)
LP receive request mask (cleared = 0)
LP DMA channel interrupt unmask (P1I) (set = 1)
LP Invalid transmit mask (cleared = 0)
External transfer done interrupt mask (cleared = 0)
Comment
Start of block 0
32-bit data transfers
×
384 32-bit transfers