Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 558

Functional Description
SRCx_TDM_IP_O
SRCx_FS_IP_I
64-BIT SERIAL INPUT
SRCx_CLK_IP_I
SHIFT PORT (SIP)
REG SMODE IN
SRCx_DAT_IP_I
PCLK/4
Figure 12-1. Sample Rate Converter Block Diagram
The FIFO receives the left and right input data and adjusts the amplitude
of the data for both the soft muting of the SRC and the scaling of the
input data by the sample rate ratio before storing the samples in RAM.
The input data is scaled by the sample rate ratio because as the FIR filter
length of the convolution increases, so does the amplitude of the convolu-
tion output. To keep the output of the FIR filter from saturating, the
input data is scaled down by multiplying it by (
when
SRCx_FS_OP
mute and stop muting the SRC.
The RAM in the FIFO is 512 words deep for both left and right channels.
An offset of 64 to the write address, provided by the
is added to prevent the RAM read pointer from overlapping the write
12-6
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SRCCTL MUTE
S/PDIF RX
Hard/Soft/Auto
DE-EMPHASIS
FILTER
<
. The FIFO also scales the input data to
SRCx_FS_IP
ADSP-214xx SHARC Processor Hardware Reference
SRCMUTE
Auto/Manual
MUTE
MUTE
OUT
IN
SAMPLE RATE
CONVERTER
(SRC) RATIO
SERIAL
SRCx_FS_OP_I
OUTPUT
PORT (SOP)
64-BIT
DITHER
SHIFT
MATCHED PHASE
REG
SMODE OUT
)/(
SRCx_FS_OP SRCx_FS_IP
SRCx_FS_IP
INTERRUPT
SRCx_DAT_OP_O
SRCx_CLK_OP_I
SRCx_TDM_OP_I
)
counter,