Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 361

Channels Complete Interrupt – This interrupt is generated when all the
channels are complete or when one iteration of time slots completes.
MAC Status Interrupt – The status interrupt sources are derived from the
register.
FIRMACSTAT
(IIRMACSTAT)" on page A-91.
Service Channel Interrupts – Based on the
register, both bits (
register if either of the conditions is met. The interrupt service
IIRDMSTAT
routine should read (to clear) both bits.
Service MAC Status Interrupts – A MAC status interrupt is generated
whenever a floating-point operation results in an arithmetic exception.
Reading the
IIRMACSTAT
exception.
Debug Features
The following sections describe the debugging features available on the
accelerator.
Local Memory Access
The contents of IIR delay line and coefficient memories are made observ-
able for debug by setting the
the
IIRDEBUGCTL
and four data registers are provided for debug operations. Bit 11 of the
this register selects coefficient memory if set (=1) and selects delay line
memory in cleared (=0).
The 40-bit wide debug mode read data register is organized as:
• The
IIRDBGRDDATA_L
• The
IIRDBGRDDATA_H
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
For more information, see "IIR MAC Status Register
or
IIR_DMAWCDONE
register returns for which MAC unit is causing an
IIR_DBGMODE
control register. The debug address register (
register holds the lower 32 bits
register holds the upper 8 bits
FFT/FIR/IIR Hardware Modules
bit in the
IIR_CCINTR
) are set in the
IIR_DMAACDONE
/ and
IIR_DBGMEM
IIRCTL1
bits in
IIR_HLD
)
IIRDBGADDR
6-65