Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 755

rupts. (By default, these interrupts are not configured in the
register—the
PICRx
This method shown in
value of the
UARTx_RXI
Listing 21-2. Enabling TWI Interrupts
bit set mode1 IRPTEN;
bit set imask P1I;
ustat1=dm(PICR0);
bit set ustat1 P1I4|P1I2|P1I1|P1I0;
bit clr ustat1 P1I3;
dm(PICR0)=ustat1;
Interrupt Sources
The six different types of interrupts used by the TWI are grouped accord-
ing to master, slave or error operation. Those used in slave operation are:
• Transfer Initiate
• Transfer Complete
and for master operation:
• Transfer Complete
• TX/RX Buffer service
and for error operation:
• Transfer Error
• Transfer Overflow
For interrupt execution, the specific
transmit bit must be enabled in the
TWITXINT
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Two Wire Interface Controller
register has to be programmed to configure them.)
Listing 21-2 uses the
or interrupts.
UARTx_TXI
/* enables global interrupts */
/* unmasks P1I interrupt */
/* route TWII 0x17 to P1I */
TWIRXINT
IRPTL
register with the code
PICR
receive bit or the specific
register. The
TWIIMASK
21-17