Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 685

Functional Description
The Shift Register module consists of an 18-stage serial shift register,
18-bit latch, and three-state output buffers. Three-state buffers are imple-
mented in I/O buffers. The shift register and latch have separate clocks.
Data is shifted on the positive-going transitions of the
The data in each flip-flop is transferred to the respective latch on a posi-
tive-going transition of the
data input (S
R_SDI_I
A common active low asynchronous reset (
18-bit shift register and for 18-bit latch. As shown in the
latch has 18 parallel outputs to drive three-state output buffers. Data in
the latch appears at the output whenever the output enable input
( ) is high. The
SR_LDOE_I
( ), and a software programmable reset (
SR_CLR
two signals goes low, then
( ) can be selected from any one of the 18-bit register's outputs.
SR_SDO_O
Selection of the source is provided through software using the
ister. A common active low asynchronous reset (
the shift register and for the latch.
ADSP-214xx SHARC Processor Hardware Reference
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input. The shift register has a serial
SR_LAT_I
) and a serial data output (
signal is derived from an external pin
SR_CLR_I
goes low. The serial data output
SR_CLR_I
Shift Register – ADSP-2147x
SR_SCLK_I
) for cascading.
SR_SDO_O
) is provided for
SR_CLR_I
Figure
). If either of these
SR_CTL1
) is provided for
SR_CLR_I
input.
17-1, the
reg-
SR_CTL
17-5