Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 925

Table A-60. MLB_SMCR Register Bit Descriptions (RW) (Cont'd)
Bit Name
4 SMSC
5 SMML
6 SMMU
31–7 Reserved
Channel Interrupt Status Register (MLB_CICR)
The channel interrupt status register reflects the channel interrupt status
of the individual logical channels. The channel status update (
set by hardware when a channel interrupt is generated. The
sticky and can only be reset by software. To clear a particular bit in this
register, software must clear all of the unmasked status bits in the corre-
sponding
MLB_CSCRx
Table A-61. MLB_CICR Register Description (RO)
Bit Name
30–0 CSU
31 Reserved
MLB Base Registers
The DMA address is constituted by a 5-bit base in the MLB base registers
(for the corresponding channel data type) and a 14-bit offset configured
using the bits in the
BCA
and offset registers use round robin arbitration to determine which logical
channel is granted access to the DMA bus.
ADSP-214xx SHARC Processor Hardware Reference
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Description
System Masks Subcommand. When set, this bit masks system interrupts
for MlbSubCmd (0xE6) system command.
System Masks MLB Lock. When set, this bit masks system interrupts
generated when MLB lock is detected. At reset, MLB lock events are
masked, (SMML = 1).
System Masks MLB Unlock. When set, this bit masks system interrupts
generated when a MediaLB unlock is detected. At reset, MediaLB unlock
events are masked (SMMU = 1).
registers.
Description
Channel Status Update.
register. The base address registers
MLB_CCBCRx
Registers Reference
) bits are
CSU
bits are
CSU
A-99