Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 742

SRU Programming
SRU Programming
The TWI signals are available through the SRU2, and are routed as
described in Table
Table 21-3. TWI DPI/SRU2 Signal Connections
Internal Node
Inputs
TWI_CLK_I
TWI_DATA_I
Outputs
TWI_CLK_PBEN_O
TWI_DATA_PBEN_O
Clocking
The fundamental timing clock of the TWI module is peripheral clock
( ). Serial clock frequencies can vary from 400 kHz to less than 20
PCLK
kHz. The resolution of the generated clock is 1/10 MHz or 100 ns.
=
CLKDIV TWI_CLOCK
For example, for an
ns) and an internal time reference of 10 MHz (period = 100 ns):
= 2500 ns ÷ 100 ns = 25
CLKDIV
For an
TWI_CLOCK
Note that
CLKLOW
21-4
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21-3.
DPI Group
Group A
Group C
period ÷ 10 MHz time reference
of 400 kHz (period = 1/400 kHz = 2500
TWI_CLOCK
with a 30% duty cycle, then
and add up to
CLKHI
ADSP-214xx SHARC Processor Hardware Reference
SRU2 Register
SRU2_INPUT0
= 17 and
CLKLOW
.
CLKDIV
= 8.
CLKHI