Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 778

Programming Models
Post Divider
Use the following procedure and the example shown in
program or reconfigure the divider.
1. Disable any peripheral (configured with
the peripherals cannot be enabled when changing VCO to core
clock ratio.
2. Select the PLLD divider by setting the PLLD bits (6–7) in the
register and enable the
PMCTL
3. Wait 15
picked up on the fly and the clocks smoothly transition to their
new values after a maximum of 14 core clock
4. Re-enable the peripherals.
Listing 22-2. Post Divider
ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP;
bit set ustat2 DIVEN|PLLD4;
dm(PMCTL) = ustat2;
lcntr = 15, do wait until lce;
wait: nop;
22-14
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cycles. During this time, the new divisor ratios are
CCLK
/* bypass disabled*/
/* set and enable post divisor */
ADSP-214xx SHARC Processor Hardware Reference
=
PCLK CCLK
bit.
DIVEN
CCLK
Listing 22-2 to
/2). Note that
cycles.