Duty Cycles - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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clock increments in a PWM period (edge aligned mode) or in a half

PWM period (center aligned mode) in half a PWM period.

Therefore, the PWM switching period, T

= 2 × PWMTM × t

For example, for a 200 MHz

switching frequency of 10 kHz (T

The largest value that can be written to the 16-bit

0xFFFF = 65,535 which corresponds to a minimum PWM switching fre-

when the PWM outputs or PWM sync is enabled.

Duty Cycles

The two 16-bit read/write duty cycle registers,

duty cycles of the four PWM output signals on the PWM pins. The

two's-complement integer value in the

cycle of the signals on the

integer value in the

two's-complement integer counts of the fundamental time unit,

define the desired on-time of the high-side PWM signal produced by the

ADSP-214xx SHARC Processor Hardware Reference

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(edge aligned)

(center aligned)

------------------------------

------------------------- -

values of 0 and 1 are not defined and should not be used

pins. The duty cycle registers are programmed in

Pulse Width Modulation

, can be written as:

and a desired PWM center aligned

= 100 μs), the correct value to load

. The two's-complement

, control the

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