Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 341

Interrupt Sources
There are two types of DMA interrupt sources associated with the acceler-
ator. The
FIR_CCINTR
Window Complete Interrupt – This interrupt is generated at the end of
each channel when all the output samples are calculated corresponding to
a window and updated index values are written back.
All Channels Complete Interrupt – This interrupt is generated when all
the channels are complete or when one iteration of time slots completes.
MAC Status Interrupt – The status interrupt sources are derived from the
register.
FIRMACSTAT
(FIRMACSTAT)" on page A-83.
Service Channel Interrupts – Based on the
register both bits (
register if either of the conditions is met. The interrupt service
FIRDMSTAT
routine should read (to clear) both bits.
Service MAC Status Interrupts – A MAC status interrupt is generated
whenever a fixed or floating-point operation results in an arithmetic
exception. Reading the
causing an exception.
Debug Features
The following sections provide information of debugging the FIR
accelerator.
Local Memory Access
The contents of FIR delay line and coefficient memories are made observ-
able for debug by setting the
the
FIRDEBUGCTL
( ) and two data registers are provided for debug operations.
FIR_DBGADDR
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit in the
FIRCTL1
For more information, see "FIR MAC Status Register
or
FIR_DMAWDONE FIR_DMAACDONE
register returns for which MAC unit is
FIRMACSTAT
FIR_DBGMODE
control register. The debug address register
FFT/FIR/IIR Hardware Modules
register controls these interrupts.
bit in the
FIR_CCINTR
) are set in the
/ and
FIR_DBGMEM
FIRCTL1
bits in
FIR_HLD
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