Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 313

One transfer control block (TCB) needs to be configured for each chan-
nel. The TCB contains:
• A control register value to configure the FFT parameters for each
channel.
• DMA parameter register values for input data.
• DMA parameter register values for twiddles load.
• DMA parameter register values for output data.
Intermediate results for large FFT are stored in the internal
memory.

The circular access type is used for large FFTs to process the entire
FFT (VxH) matrix.
Buffer Length
Register
Figure 6-2. Circular Buffer Addressing
Interrupts
The FFT accelerator has two interrupts that are programmable through
the programmable interrupt priority control register (see
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
FFT/FIR/IIR Hardware Modules
20
19
.
.
.
5 Index Register
4
3
2
1 Base Register
Appendix B,
6-17