Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 543

These are sticky bits that must be cleared by writing to the
(bit 6 of the
IDP_CTL0
from IDP channels is not accepted into the FIFO, and data values are lost.
New data is only accepted once space is again created in the FIFO.
Interrupts
This section describes the different types of interrupts used by the inter-
face. Table 11-9
Table 11-9. IDP Interrupt Overview
Interrupt Interrupt Condition
Sources
DAI IDP – DMA RX done
(I2S, left/right – Core RX buffer size
justified, TDM, exceeded
8 channels) – RX buffer overflow
error
Interrupt Acknowledge
The correct handling of the IDP interrupt requires that the ISR must read
the
DAI_IMASK_x
that many interrupts are combined in the DAI interrupt. Refer to
rupts" on page
Threshold Interrupts
When using the interrupt scheme, the
register) can be set to N, so N + 1 data can be read from the
IDP_CTL0
FIFO in the interrupt service routine (ISR). The
register allows to fire flexible interrupts in order to respond
DAI_IMASK_X
with the core under different system conditions.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register). When an overflow occurs, incoming data
provides an overview of IDP interrupts.
Interrupt
Completion
Internal transfer
completion
register to clear the interrupt latch appropriately. Note
9-32.
Input Data Port
Interrupt
Acknowledge
Read-to-clear
DAI_IMASK_x
+ RTI instruc-
tion
bits (bits 3-0 of the
IDP_NSET
IDP_FIFO_GTN_INT
bit
IDP_CLROVR
Default IVT
P0I, P12I
"Inter-
bit in
11-23