Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 764

Table of Contents

Electrical Specifications

The tasks performed at each interrupt are:

This interrupt is generated due to the arrival of one or two data

bytes into the receive FIFO. The

time (or earlier) and

direction of the next transfer. The

before the addressing phase of the subsequent transfer begins.

This interrupt has occurred due to the completion of the data

receive transfer. At this time the data transmit transfer begins. The

transmitted. Clear the

This interrupt is generated when there is one or two bytes of empty

space in the FIFO. Simple data handling is all that is required.

The transfer is complete.

Electrical Specifications

All logic complies with the electrical specification outlined in the Philips

C Bus Specification version 2.1 dated January, 2000.

www.BDTIC.com/ADI

should be cleared to reflect the change in

field should be set to reflect the number of bytes to be

ADSP-214xx SHARC Processor Hardware Reference

bit should be set at this

bit must be cleared

bit if this is the last transfer.

Chapters

Table of Contents