Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 559

RIGHT DATA IN
LEFT DATA IN
SRCx_FS_IP
COUNTER
SRCx_FS_IP
SRCx_FS_OP
Figure 12-2. Sample Rate Converter Architecture
address. This offset value is useful for applications when small changes in
the sample rate ratio between
The maximum decimation rate can be calculated from the RAM word
depth is (512 – 64) ÷ 64 taps = 7.
The digital-servo loop is essentially a ramp filter that provides the initial
pointer to the address in RAM and ROM for the start of the FIR convolu-
tion. The RAM pointer is the integer output of the ramp filter while the
ROM pointer is the fractional part. The digital-servo loop must be able to
provide excellent rejection of jitter on the
clocks as well as measure the arrival of the
ps. The digital-servo loop also divides the fractional part of the ramp out-
put by the ratio of (
>
SRCx_FS_IP SRCx_FS_OP
The digital-servo loop is implemented with a multi-rate filter. To settle
the digital-servo loop filter quickly at startup or at a change in the sample
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Asynchronous Sample Rate Converter
FIFO
DIGITAL
SERVO LOOP
SAMPLE RATE RATIO
SAMPLE RATE
RATIO
EXTERNAL RATIO
(MATCHED PHASE MODE)
SRCx_FS_IP
)/(
SRCx_FS_IP SRCx_FS_OP
, to dynamically alter the ROM coefficients.
ROM A
HIGH
ROM B
ORDER
INTERPOLATION
ROM C
ROM D
FIR FILTER
SRCx_DAT_OP
and are expected.
SRCx_FS_OP
and
SRCx_FS_IP SRCx_FS_OP
clock within 4.97
SRCx_FS_OP
) for the case when
12-7