Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 748

Functional Description
TWI_CLOCK (BUS)
TWI CONTROLLER
DATA
SECOND MASTER
DATA
TWI_DATA (BUS)
Figure 21-5. TWI Bus Arbitration
Start and Stop Conditions
Start and stop conditions involve serial data transitions while the serial
clock is at logic 1 level. The TWI controller generates and recognizes these
transitions. Typically, start and stop conditions occur at the beginning
and at the conclusion of a transmission, with the exception of repeated
start "combined" transfers, as shown in
TWI_CLOCK (BUS)
TWI_DATA (BUS)
START
Figure 21-6. TWI Start and Stop Conditions
21-10
www.BDTIC.com/ADI
START
ADSP-214xx SHARC Processor Hardware Reference
ARBITRATION
LOST
Figure 21-6.
STOP