Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 359

• A control register value to configure the filter parameters for each
channel
• DMA parameter register values for the input data (delay line)
• DMA parameter register values for coefficient load
• DMA parameter register values for output data
As shown in "IIR Accelerator TCB" on page 2-17
accelerator loads the TCB into its internal registers and uses these values
to fetch coefficients and data and to store results. After processing a win-
dow of data for any channel, the accelerator writes back the
index register) and
memory, so that data processing can begin from where it left off during
the next time slot of that channel.
Buffer Length
Register
Figure 6-13. Circular Buffer Addressing
For 32-bit mode, the write back values for the index registers is equal to
+ W and
IIRII
For 40-bit mode, the write back values are:
+ 2 × W and
IIRII
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
(output index register) values to the TCB in
IIROI
+ W.
IIROI
+ 2 × W.
IIR0I
FFT/FIR/IIR Hardware Modules
and Figure
20
19
.
.
.
5 Index Register
4
3
2
1 Base Register
6-7, the
(input
IIRII
6-63