Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 614

Programming Model
Input clock through SRU
• If divisor is 0 or 1 (bypassed) the latency can vary from 0 to 1 input
clock period. For example if the input clock has a period of 100 ns
then this latency can be a maximum of 100 ns.
• For other divisor values the latency can vary between 2 to 3 input
clock periods. For example if the input clock has a period of 100 ns
then this latency can be between 200 and 300 ns.
Programming Model
The section describes which sequences of software steps required for suc-
cessful PCG operation.
Frame Sync Phase Setting
The phase unit requires that the clock and FS is enabled simultaneously in
an atomic instruction.
1. Write the clock divider/low 10-bit Phase divider to
register.
2. Program the FS divider/high 10-bit Phase divider, enable both the
and
ENCLKx
Note that both units must be disabled in the same way.
External Event Trigger
The trigger with the external clock is enabled by setting bits 0 and 16 of
the register. The phase must be programmed to 3, so that the
PCG_SYNC
rising edge of the external clock is in sync with the frame sync
(Figure 14-5).
14-20
www.BDTIC.com/ADI
bits in the
ENFSx PCG_CTLx0
ADSP-214xx SHARC Processor Hardware Reference
PCG_CTLx1
registers.