Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 552

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Programming Model

6. Re-enable the

7. Exit the ISR.

If a zero is read in step 5 (no more interrupts are latched), then all of the

interrupts needed for that ISR have been serviced. If another DMA com-

pletes after step 5 (that is, during steps 6 or 7), as soon as the ISR

completes, the ISR is called again because the OR of the latched bits will

not be nonzero again. DMAs in process run to completion.

If step 5 is not performed, and a DMA channel expires during step

4, then, when IDP DMA is re-enabled, (step 6) the completed

DMA is not reprogrammed and its buffer overruns.

This unit is multiplexed with SIP0. The PDAP provides one clock

input, one clock hold input and a maximum of 20 parallel data

input pins. The positive or negative edge of the clock input is used

for data latching. The clock hold input (

clock edge—if this input is high then clock edge is masked for data

latching. It supports four types of data packing mode selected by

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ADSP-214xx SHARC Processor Hardware Reference

) validates a

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