Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 682

Features
Table 17-1. Shift Register Specifications (Cont'd)
Feature
Access Type
Data Buffer
Core Data Access
DMA Data Access
DMA Channels
DMA Chaining
Boot Capable
Local Memory
Clock Operation
Features
The following list describes the features of the shift register.
• 18-stage serial/parallel shift register
• 18-bit parallel data latch
• 18 parallel output signals (
• Serial data input (
ing of multiple SR registers
• SRU routing unit allows the input selection for clock and data
from
SPORT7-0
• Pin buffers remain three-stated coming out of reset until config-
ured by software as outputs
17-2
www.BDTIC.com/ADI
Availability
Yes
N/A
N/A
N/A
N/A
N/A
No
f /4
PCLK
SR_LDO17-0
) and output pins (
SR_SDI
, , DAI Pin buffer 8–1 or external SR pins
PCGA-B
ADSP-214xx SHARC Processor Hardware Reference
) with can be three-stated
) allows cascad-
SR_SDO