Frame Sync; Sampling Edge; Frame Sync And Data Sampling - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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Functional Description

When the SPORT is configured as a receiver (

fers are activated. The receive buffers act like a three-location FIFO

because they have two data registers plus an input shift register.

Frame Sync

The following sections provide information on frame syncs which applies

to the SPORTs in all operating modes. For mode specific frame sync

information, see

Data and frame syncs can be sampled on the rising or falling edges of the

serial port clock signals. The

the sampling edge. For sampling receive data and frame syncs, setting

is cleared (=0), the processor selects the falling edge of

for sampling receive data and frame syncs.

Note that transmit data and frame sync signals change their state on the

clock edge that is not selected. For example, the transmit and receive func-

tions of any two serial ports connected together should always select the

same value for

and received signals are sampled on the opposite edge.

The information contained in this section is generic to the SPORTs in any

operating mode. Additional information about frame syncs and data sam-

pling that applies to a specific operating mode can be found in

Modes" on page

www.BDTIC.com/ADI

"Operation Modes" on page

so internally-generated signals are driven on one edge

ADSP-214xx SHARC Processor Hardware Reference

= 0), the receive buf-

control registers selects

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