Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 502

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Data Transfers

Frame Sync Generation

The frame syncs are generated if the transmit or receive buffers are

updated according to the

by the core, the frame sync out is not driven off-chip and data output is

If both A and B channels are enabled, one of the following can occur.

• In standard mode the

the conditions of whether both channels are logically ANDed or

• For all other operating modes, channels A and B are logically

ANDed. If both channels are enabled, both buffers need to be

updated to drive data and frame sync off-chip.

Note that for all operating modes, if the

overriden. The frame sync is driven off-chip and the data output are zero

Internal Memory DMA Transfers

SPORT DMA provides a mechanism for receiving or transmitting an

entire block of serial data before the interrupt is generated. When serial

port DMA is not enabled, the SPORT generates an interrupt every time it

receives or starts to transmit a data word. The processor's on-chip DMA

controller handles the DMA transfer, allowing the processor core to con-

tinue running until the entire block of data is transmitted or received.

Service routines can then operate on the block of data rather than on sin-

gle words, significantly reducing overhead.

Therefore, set the direction bit, the serial port enable bit, and DMA

Enable bits before initiating any operations on the SPORT data buffers. If

the processor operates on the inactive transmit or receive buffers while the

SPORT is enabled, it can cause unpredictable results.

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bit setting (=0). If there is no buffer update

ADSP-214xx SHARC Processor Hardware Reference

bit is set, all conditions are

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