Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 642

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(bit 12) in the

(set = 1) the

bits, see the SHARC Processor Programming Reference.

When using DMA transfers, programs must also specify whether to gener-

ate interrupts based on transfer or error status. For DMA transfer status

based interrupts, set the

upon the state of

nal count becomes zero or the external transfer is complete. Otherwise, set

bit to trigger the interrupt if one of the error conditions occurs

during the transmission—for example a multimaster error (

buffer underflow (

During core-driven transfers, the

do not generate interrupts.

When DMA is disabled, the processor core may read from the

ter or write to the

memory-mapped IOP registers. A maskable interrupt is generated when

the receive buffer is not empty or the transmit buffer is not full. The

error conditions do not generate interrupts in these modes.

Multi Master Error

bit (1) is set when the

enabled as a master is driven low by some other device in the system. This

occurs in multimaster systems when another device is also trying to be the

To enable this feature, set the

this error is detected, the following actions are taken:

interface as a slave.

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bit (bit 19) in the

bit the interrupt can be generated when the inter-

data buffer. The

control bit in

ADSP-214xx SHARC Processor Hardware Reference

= 0), or receive buffer overflow

input pin of a device that is

is cleared, configuring the SPI

error conditions

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