Ddr2 Commands; Load Mode Register - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

For read commands, there is a latency from the start of the read command
to the availability of data from the DDR2, equal to the CAS latency. This
latency is always present for any single read transfer. Subsequent reads do
not have latency. Note that writes also have latency which is = read latency
– 1. For more information on commands used by the DDR2 controller,
see "SDRAM Commands"

DDR2 memory accesses are burst oriented per the JEDEC specifi-
cation. The burst accesses are NOT divisible and therefore every
DDR2 access needs to satisfy the burst length of 4 words (4x16)
even if not required for an application. This makes single
read/write accesses inefficient since the controller needs to mask
unwanted data.

DDR2 Commands

This section provides a description of each of the commands that the
DDR2 controller uses to manage the DDR2 interface. These commands
are handled automatically by the DDR2 controller. A summary of the var-
ious commands, including the truth tables used by the on-chip controller
for the DDR2 interface can be found in the JEDEC specification
(JESD79-2C).

Load Mode Register

This command initializes DDR2 operation parameters and controls part
of the power-up sequence, initiated by writing 1 to the
DDR2 memory control register (
register are loaded into the
DDR2CTL0
command uses the address bus of the DDR2 for data input.
The load mode register command initializes the following parameters.
• Bits 2–0 – Burst length = 4
• Bit 3 – Wrap type (BT) = sequential (always zero)
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
below.
). Values written into the
DDR2CTL2
register during power up. The
MR
External Port
bit in the
DDR2PSS
3-51