Pin Buffer Input; Pin Buffer Enable - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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Functional Description

Table 9-5. DPI Routing Capabilities (Cont'd)

Input (xxxx_I)

C–Pin Buffer

DPI Pin Buffer Enable

Pin Buffer Input

DAI group D or DPI group B are used to specify any signals that are

driven off-chip by the pin buffers. A pin buffer input (

an output from the processor when the pin buffer enable is set (= 1).

Each physical pin (connected to a bonded pad) may be connected via the

SRU to any of the outputs of the DAI/DPI peripherals, based on the bit

field values. The SRU also may be used to route signals that control the

pins in other ways. Many signals may be configured for use as control

Any of the DAI/DPI pins may also be considered general-purpose

input/output (GPIO) pins. Each of the DAI pins can also be set to drive a

high or low logic level to assert signals. They can also be used as DAI/DPI

interrupt sources.

On the DAI, two dedicated input pin buffers are allowed to invert the

input level on the pins by a bit setting. However this only applies if the

buffer is not assigned to itself.

DAI group F or DPI group C signals are used to specify whether each

DAI/DPI pin is used as an output or an input by setting the source for the

pin buffer enables. When a pin buffer enable (

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Output (xxxx_O)

SPI (MOSI, MISO, DS, CLK)

SPIB (MOSI, MISO, DS, CLK)

TWI (clock, data)

ADSP-214xx SHARC Processor Hardware Reference

Logic level high

Logic level low

) is driven as

) is set (= 1), the

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