Changing The Vco Clock During Runtime - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Programming Models
4. Self refresh mode-no activities on all SDRAM signals (clock
optional).
5. Clear the
6. SDRAM access releases controller from self-refresh mode.

Changing the VCO Clock During Runtime

In previous SHARC models, only a hardware reset initiated another
SDRAM power-up sequence. This is no longer the case since the PLL
allows programs to change the output clocks during runtime.
All SDRAM timing specifications are normalized to the SDRAM clock.
Since most of these are minimum specifications, (except t
maximum specification), a variation of the system clock violates a specific
specification and causes a performance degradation for the other
specifications.
The reduction of the system clock violates the minimum specifications,
while increasing the system clock violates the maximum t
specification. Therefore, careful software control is required to adapt these
changes. Therefore, the release from self-refresh mode should be a dummy
read operation since it happens with the old frequency settings.

For most applications, the SDRAM power-up sequence and writ-
ing of the mode register needs to occur only once. Once the
power-up sequence has completed, the
again unless a change to the mode register is desired.
The recommended procedure for changing the system frequency
as follows.
1. Set the SDRAM to self-refresh mode by writing a 1 to the
of the
SDCTL
2. Poll the
3-128
www.BDTIC.com/ADI
bit to re-enable
DSDCTL
register.
bit of
SDSRA SDSTAT
ADSP-214xx SHARC Processor Hardware Reference
(optional).
SDCLK
bit should not be set
SDPSS
register for self-refresh grant.
, which is a
REF
REF
is
SDCLK
bit
SDSRF