Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 607

Bypass Mode
When the frame sync divisor for the frame sync has a value of zero or one,
the frame sync is in bypass mode, and the
functionality than in normal mode.

In normal mode bits 15–0 and 31–18 of the
used to program the pulse width count. In bypass mode bits 15–2
and 31–18 are ignored. Bits 1–0 and 17–16 are renamed to
STROBEx
below.
If the bit of
STROBEx
passed (see Figure
inverted, depending on the
CLOCK INPUT
FOR FRAME SYNC
FRAME SYNC OUTPUT
(INVFSA = 0, STROBEA = 0)
FRAME SYNC OUTPUT
(INVFSA = 1, STROBEA = 0)
Figure 14-3. Bypass and Inverted Bypass
One-Shot Mode
In one-shot mode operation, the PCG produces a series of periods but
does not run continuously.
Bypass mode also enables the generation of a strobe pulse (one shot frame
sync). Strobe usage ignores the divider counters and looks to the SRU to
provide the input signal. Two bit fields determine the operation in this
mode.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
and respectively. This is described in more detail
INFSx
register is cleared, then the input is directly
PCG_PWx
14-3) to the frame sync output either inverted or not
INVFSx
Precision Clock Generator
registers have different
PCG_PWx
PCG_PWx
bit of the registers.
PCG_PWx
registers are
14-13