Clocking; Functional Description - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

IIR Accelerator
DMA Status (IIRDMASTAT). Provides the status of accelerator opera-
tion including chain pointer loading, coefficient DMA, processing
progress, window complete and all channels complete.
MAC Status (IIRMACSTAT). TProvides the status of the MAC
operations.
Debug Mode Control (IIRDEBUGCTL). Controls the debug mode
operation of the accelerator.

Clocking

The IIR accelerator runs at the maximum speed of the peripheral clock
(f ).
PCLK

Functional Description

Figure 6-9 shows the block diagram of the IIR hardware accelerator. The
accelerator has a coefficient memory size of 1440 x 40 bits, a data memory
size of 576 x 40 bits and one MAC unit with an input data buffer to sup-
ply data to the MAC.
6-56
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ADSP-214xx SHARC Processor Hardware Reference