Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 602

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Functional Description

Divider Mode Selection

If frame sync divisor > 1 the PCG frame sync output frequency is equal to

the input clock frequency, divided by a 20-bit integer. This integer is

specified in the

However if the frame sync divisor is zero or one, the PCG's frame sync

clock generation unit is bypassed, and the frame sync input is connected

directly to the frame sync output. For

have different functionality than in normal mode.

Phase shift is a frame sync parameter that defines the phase shift of the

frame sync with respect to the input clock of the same unit. This feature

allows shifting of the frame sync signal in time relative to the clock input

signal. Frame sync phase shifting is often required by peripherals that need

a frame sync signal to lead or lag a clock signal.

For example, the I

high to low occur one clock cycle before the beginning of a frame. Since

S frame is 64 clock cycles long, delaying the frame sync by 63 cycles

produces the required framing.

Phase shifting is represented as a full 20-bit value so that even when the

frame sync is divided by the maximum amount, the phase can be shifted

to the full range, from zero to one input clock short of the period.

Phase shifting is specified as a 2 x 10-bit divider value in the

A single 20-bit value spans these two bit fields. The upper half of the word

(bits 19–10) is in the

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bit field (bits 19–0 of the

S protocol specifies that the frame sync transition from

bit field (bits 29–20) of the

ADSP-214xx SHARC Processor Hardware Reference

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