Ddr2 Controller; Power-Up Sequence - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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3. Execute the desired PLL programming sequence.

mation, see "PLL Start-Up" on page

4. Wait 4096

PLL has settled to the new frequency.

5. Reprogram the SDRAM registers (

priate to the new

6. Bring the SDRAM out of self-refresh mode by performing a

dummy read SDRAM access.

7. The SDC now issues the commands

ize the SDC and the SDRAM to the new frequency.

The SDRAM device is now ready to be accessed.

DDR2 Controller

The following sections are specific to DDR2 SDRAM memory on the

ADSP-2146x processor.

The following steps are used to power-up the DDR2 device.

1. Ensure the minimum DDR2 clock frequency is stable and at least

125 MHz (according to datasheet).

2. Program the core to DDR2 clock ratio using the

PLL changes wait at least 4096 core cycles, for output divider

changes at least 15 core clock cycles for effect latency.

3. If a new frequency is desired, put the on-chip DLL into reset using

4. Wait at least 9 core cycles for the DLL to lock to a new frequency.

ADSP-214xx SHARC Processor Hardware Reference

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frequency and assure that the

External Port

(For more infor-

asserted) which indicates the

) with values appro-

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