Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 497

Timing Control Bits
Several bits in the
• Internal Clock (
• Internal Frame Sync (
• Sampling Edges Frame Sync/Data (
• Selecting Channel Order (
• Word Length (
• Word Order (
• Word Packing (
The following bits in the
options in packed mode.
• Frame Delay (
• Number of multichannel channels (
Data Transfers
Serial port data can be transferred for use by the processor in two different
methods:
• Core-driven single word transfers
• DMA transfers between both internal and external memory
DMA transfers can be set up to transfer a configurable number of serial
words between the serial port buffers (
) and internal memory automatically. Core-driven transfers use
RXSPxB
SPORT interrupts to signal the processor core to perform single word
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register enable and configure packed mode.
SPCTLx
)
ICLK
)
IFS
L_FIRST
, 8–32 bits)
SLEN
)
LSBF
)
PACK
register are used to configure timing
SPMCTLx
)
MFD
)
CKRE
)
)
NCH
, ,
TXSPxA TXSPxB RXSPxA
Serial Ports
, and
10-39