Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 721

Serial Communication
The UART follows an asynchronous serial communication protocol with
these options:
• 5 – 8 data bits
• 1 or 2 stop bits
• None, even, or odd parity
• Baud rate = PCLK/(16 × divisor), divisor value can be from 1 to
65,536
All data words require a start bit and at least one stop bit. With the
optional parity bit, this creates a 7 to 12-bit range for each word. The
format of received and transmitted character frames is controlled by the
line control register (
least significant bit (LSB) first.
Figure 20-2 shows a typical physical bit stream measured on the transmit
pin.
START BIT LSB
Figure 20-2. Bit Stream on the Transmit Pin
Transmit and receive channels are both buffered. The
buffers the transmit shift register (
fers the receive shift register (
accessible by software.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
). Data is always transmitted and received
UARTLCR
DATA BITS
D0 D1 D2 D3 D4 D5
UARTTSR
). The shift registers are not directly
UARTRSR
UART Port Controller
STOP BIT(S)
D6 D7
PARITY BIT (OPTIONAL, ODD OR EVEN)
UARTTHR
) and the
UARTRBR
register
register buf-
20-7